By Pierre-Camille Lacaze, Jean-Claude Lacroix
Written for scientists, researchers, and engineers, Non-volatile Memories describes the new examine and implementations in terms of the layout of a brand new iteration of non-volatile digital stories. the target is to exchange latest stories (DRAM, SRAM, EEPROM, Flash, etc.) with a common reminiscence version more likely to achieve larger performances than the present varieties of reminiscence: super excessive commutation speeds, excessive implantation densities and retention time of knowledge of approximately ten years.
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E. 10–100 pJ). It must be recalled that the energy consumption for writing a bit in the case of SRAMs and DRAMs is only 5 × 10-4 and 5 × 10-3 pJ, respectively [YAN 13]. 3. Multilevel cells The previously described floating gate MOSFETs run according to the absence or presence of a charge in FG corresponding to the two values ‘0’ and ‘1’ of a bit. Such a memory is described as a “single level cell” (SLC) memory. Recently, in an attempt to increase integration density, several manufacturers have developed floating gate memories in which, instead of considering only two levels of charge storage (‘0’ and ‘1’) corresponding to two separate values, VTh,0 and VTh,1, several storage levels are defined, which lead to several operating thresholds, and, consequently, memories with several bits, described as “multilevel cells” (MLC) memories.
5 billion, whereas the market for NAND Flash, that was negligible in 2000 (370 million dollars), has considerably and almost constantly increased, 14 billion dollars in 2009 [WON 13], an evolution corresponding to the explosion in the use of smartphones and other portable devices, which are important NAND Flash consumers. 42 Non-volatile Memories in the 2000s and, despite the fact that it is still high, it is getting closer to that of HDDs with a global turnover of over 20 billion dollars in 201212.
6). This shift, which increases with the charge, occurs toward positive or negative voltages depending on whether SC is n- or p-type. In the absence of charge in the floating gate, the transfer curve indicating the drain current IDS variation with the control gate voltage VGS is characterized by a threshold operating voltage equal to VTh(1). This threshold voltage is shifted toward positive voltages and is equal to VTh(0) when the floating gate acquires a negative charge. When a VGS between VTh(1) and VTh(0) is applied to the control gate, the two memory states are read by measuring IDS: a high current IDS corresponding to the absence of a charge in the floating gate, defines the ‘1’ state whereas a low current intensity, resulting from a negative charge, defines the ‘0’ state.